This invention relates to electrical circuits for high speed latches and multiplexers that use relatively low voltages.
CMOS CML designs for latches and multiplexers (MUXes) ARE widely used in VLSI chip design, due to the high switching speeds available with such designs. Conventional CMOS CML latch and MUX designs use three-layer staggered transistors involving a current source transistor, a switch transistor and a differential transistor pair, plus a resistive load. Advanced CMOS technology provides high switching speed capability, if sufficient voltage headroom is available to drive the transistors from a first state to a second state. However, the low voltage supply, as low as 1.2 volts for 0.13 xcexcm deep sub-micron technology, associated with state-of-the-art CMOS technology severely limits the use of conventional three-layer staggered transistor designs, unless the headroom can be increased. Where only 1.2 v is available, top to bottom, to drive a system, a conventional approach provides headroom of only about 0.2 v, which produces a sluggish response from a CMOS transistor. The response often forces the transistor to operate in the linear region, rather than in the saturated region where high(er) switching speed is available.
A conventional approach to this problem is to continue using a three-layer staggered transistor configuration, but with lowered threshold voltage Vth, and to optimize the circuit to attempt to coax another tenth of a volt out of the system to add to the (anemic) headroom. This is not a satisfactory solution, for at least two reasons. First, the extra tenth of a volt, added to headroom, does not fully restore operation of the transistor configuration in the saturation region. Second, use of a lowered threshold voltage carries with it some problems of increased instability and uncertainty in control of the circuit.
What is needed is a different approach that provides adequate headroom, preferably at least 0.3-0.5 v, without reducing voltage threshold and without wholesale modification of the latch or MUX circuit. Preferably, the approach should be flexible enough to be usable in other related circuits as well.
These needs are met by the invention, which provides an approach that reduces the additive dc voltage associated with a multi-layer staggered transistor configuration and converts a three-layer structure to what is effectively a two-layer structure for purposes of providing headroom. The system includes at least one pair of capacitors, strategically placed to isolate a dc bias associated with a transistor pair and to thereby provide additional headroom of 0.3-0.4 v to drive a transistor configuration into saturation for high speed switching.